In FIG. 25, there is shown an equivalent circuit of a static random access memory (SRAM) cell as a conventional semiconductor memory device. The conventional SRAM cell is constituted by 6 elements, i.e., access transistors Q1 and Q2, driver transistors Q3 and Q4 and load elements R1 and R2. Bit lines BL and a word line WL are connected to the access transistors Q1 and Q2, and a power-source line Vcc is connected to the load elements R1 and R2.
The conventional memory cell, however, cannot operate well when the column current is reduced due to a reduced power-source voltage. As shown in FIG. 26, there has been proposed a memory cell where bipolar transistors Q5 and Q6 are connected to the access transistors Q1 and Q2 to amplify the column current.
In the case of a memory cell such as shown in FIG. 26, the number of elements is increased from the conventional 6 elements to 8 elements, so that the memory cell area tends to be increased. Therefore, a technique is desired which forms the bipolar transistor Q5 and Q6 in the memory cell without increasing the memory cell area.